1. Field of the Invention
The present invention relates to a latch type sense amplifier circuit suitable for a static random access memory which operates with a low power supply voltage, and more particularly, to a latch type sense amplifier circuit which is less prone to be affected by variation in characteristics of elements of the circuit.
2. Description of the Related Art
Generally, a current mirror type sense amplifier circuit is used in a conventional semiconductor integrated circuit including a static random access memory (SRAM, hereinafter). The current mirror type sense amplifier stably operates, but its power consumption is large, and this circuit has difficulty in its operating characteristics with low power supply voltage. For this reason, in recent years, the need for reducing the power consumption is increasing as penetration of portable devices increases and especially, a sense amplifier circuit capable of operating with a low power supply voltage is needed.
To meet this need, there has been proposed a latch type sense amplifier circuit capable of operating at a high speed with a low power supply voltage. FIG. 1 is a circuit diagram showing a conventional latch type sense amplifier circuit.
In the conventional latch type sense amplifier circuit, a latch circuit comprises two P-channel MOS transistors MP11 and MP12 as well as two N-channel MOS transistors MN11 and MN12. The two P-channel MOS transistors MP11 and MP12 as well as the two N-channel MOS transistors MN11 and MN12 are designed such that their transistor characteristics are the same for increasing the speed of the sensing operation. More specifically, gate lengths and gate widths of the two P-channel MOS transistors MP11 and MP12 as well as those of the two N-channel MOS transistors MN11 and MN12 are set equal to each other. Logical threshold values of two inverter circuits constituting the latch circuit are set equal to each other.
Further, in the conventional latch type sense amplifier circuit, there is provided a P-channel MOS transistor MP13 connected between a bit line to which a signal D read from a memory cell is transmitted and drains of the transistors MP11 and MN11. In the conventional latch type sense amplifier circuit, there is provided a P-channel MOS transistor MP14 connected between a bit line to which a signal DB read from a memory cell is transmitted and drains of the transistors MP12 and MN12. Further, there is provided an N-channel MOS transistor MN13 connected between a grounding and sources of the transistors MNI1 and MN12. In this manner, in the conventional latch type sense amplifier circuit, one latch circuit is provided for one set of bit lines.
In the conventional latch type sense amplifier circuit thus constituted, ON and OFF of the transistors MP13 and MP14 are switched by a sense amplifier enable signal SAE, thereby controlling the operation of the circuit. The circuit can sense data at high speed with an extremely small potential difference between the pair of bit lines (D and DB).
On the other hand, as the future small-sizing tendency of the device and process technique grows, there is a tendency that the power supply voltage is lowered, the absolute value of the threshold voltage value of MOS transistors to be used is lowered, and OFF current is increased. Further, if a variation in characteristics of the MOS transistors is large, a variation in potential of the pair of bit lines (D and DB) after the rise of the word line largely depends on leak current characteristics of OFF state of a transistor in the SRAM cell connected to non-selected word line. That is, a rate of noise included in a potential difference between the pair of bit lines (D and DB) appearing after the rise of the word line is increased. Therefore, it is necessary to judge whether the potential difference between the pair of bit lines (D and DB) appearing at the time of sensing is significant.
There has been proposed a sense amplifier circuit for a RAM including a pair of latch circuits (Japanese patent Application Laid-open No. 9-22597). The sense amplifier circuit described in this publication is provided with two latch circuits having different reading speeds with respect to power supply voltage, and with a circuit for taking OR logic values of signals output from the latch circuits. A signal of a bit line is input to a gate of an N-channel MOS transistor of one of the latch circuit, and a signal of a bit line is input to a gate of a P-channel MOS transistor of the other latch circuit.
In the conventional sense amplifier circuit constituted in this manner, even when the power supply voltage is varied, it is possible to perform reading-out at a high speed.
However, in both the conventional sense amplifier circuits having one latch circuit and the sense amplifier circuit described in Japanese patent Application Laid-open No. 9-22597, there is a problem that the circuits are prone to be affected by variation in characteristics of elements.
Further, the conventional sense amplifier circuits do not have means for judging whether a normal detection of the potential difference between the pair of significant bit lines has been completed, and the circuits do not have function for detecting reading error. Therefore, there is a problem that the circuits do not have means for transmitting an again-sensing requirement when the potential difference between the pair of bit lines is insufficient.